Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame

ABSTRACT

A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, and the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame. At least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode conducts with the via. The support frame eliminates the need for a carrier wafer in the process steps.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is cross-referenced to and claims the benefit from U.S.Provisional Patent Application 60/832,317 filed Jul. 20, 2006, which ishereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

The present invention was supported in part by grant number CA099059from the NIH. The U.S. Government has certain rights in the invention.

FIELD OF THE INVENTION

The invention relates generally to ultrasonic transducers. Moreparticularly, the invention relates to one-dimensional andtwo-dimensional trench isolated capacitive micro-machined ultrasonictransducer (CMUT) arrays built on a silicon-on-insulator (SOI) waferhaving a supporting mesh frame using either wafer-bonding or sacrificialrelease methods.

BACKGROUND

In large, fully populated 1D and 2D transducer arrays, providingconnection to each array element is a challenge. In the case of 2D CMUTarrays, researchers have reported on interconnect techniques both basedon through-wafer vias and through wafer trench isolation. In thethrough-wafer via implementation, a conductive material, usually dopedpolysilicon, is used to fill the vias and serves as the conductorbetween the front and back sides of the array elements. It was foundthat after the deposition of the polysilicon, performing wafer-to-waferfusion bonding is difficult. Therefore, the through-wafer via approachis limited to only surface micromachining CMUT processes.

It has further been reported that in the trench isolation process, acarrier wafer is required during the deep reactive ion etching (DRIE)and the flip-chip bonding steps to provide the mechanical support forthe membranes. This particular requirement presents certain drawbacks inprocessing. Good adhesion between the carrier wafer and the membranesurface is required for adequate mechanical support for the membranes.However, it is difficult to separate the carrier wafer and the membraneafter the flip-chip bonding. The adhesive material may also swell in thesolvent, creating stress that can break the CMUT membranes. It is highlydesirable to eliminate the need of the carrier wafer for the trenchisolation process.

SUMMARY OF THE INVENTION

A trench-isolated CMUT array with a supporting mesh frame for fullypopulated 1D and 2D arrays is provided. According to the currentinvention, the CMUT array is built on a silicon-on-insulator (SOI)wafer. Electrical interconnections to array elements are providedthrough the highly conductive silicon substrate. Neighboring arrayelements are separated from one another by trenches on both the devicelayer and the bulk silicon. A mechanically supporting frame is designedas a mesh structure between the silicon pillars providing electricalconnections to the individual elements. The framed trench isolation iscompatible with both wafer-bonded and surface-micromachined CMUTs. Theinvention eliminates the need for attaching the device wafer to acarrier wafer for the required mechanical support during the deep trenchetching and flip-chip bonding steps, which presents difficulties duringthe release of the carrier wafer.

According to one aspect of the invention, a one-dimensional or atwo-dimensional capacitive micro-machined ultrasonic transducer (CMUT)array with supporting frame has at least three CMUT array elementsdeposited on a conductive substrate. The invention also has at least oneCMUT cell in the array element, a conductive top layer deposited to atop side of the element, and a conductive via disposed within theelements. The via is isolated from the conductive top layer and conductswith the substrate. There are at least two isolation trenches in theconductive substrate, wherein the trenches are disposed between adjacentvias to conductively isolating the vias. A substrate region between thetrenches forms a mechanical support frame, and at least one conductiveelectrode is deposited to a bottom surface of the conductive substrate,where the electrode is disposed to conduct with the via.

In another aspect of the invention, the conductive substrate has asilicon-on-insulator wafer, where the wafer includes a silicon oxidelayer on a silicon layer.

In a further aspect of the invention, the conductive top layer is aconductive material such as aluminum, titanium, tungsten or polysilicon.

In one aspect of the invention, the conductive top layer can be omittedwhen the top side of the element is as highly conductive siliconmembrane.

In a further aspect of the invention, the conductive via is a conductivematerial such as aluminum, polysilicon or amorphous silicon.

In yet another aspect, the conductive electrode can be copper, titanium,gold, platinum, aluminum or nickel.

The current invention includes a method of fabricating a one-dimensionalor two-dimensional capacitive micro-machined ultrasonic transducer(CMUT) array with supporting frame. The method includes the steps ofproviding a double-side-polished silicon-on-insulator wafer, etchingCMUT cavities in a device layer of the wafer using oxidation andbuffered oxide etching methods, electrically dividing front electricalpads on the wafer using deep reactive ion etching, bonding a secondsilicon-on-insulator wafer to the etched device layer, removing a handlelayer of the second silicon-on-insulator wafer, providing a contact viaon each array element of the CMUT array using photo lithography and wetetching or dry etching, depositing a conductive top electrode materialon the etched wafer, removing the conductive material around the vias toseparate front and back electrodes from each other, etchingthrough-wafer trenches on the silicon wafer for electrical isolation andto define a supporting frame, patterning signal electrodes on the backelectrodes, and flip-chip bonding CMUT arrays to appropriate electroniccircuits or printed circuit boards.

In one aspect of the method of fabricating a one-dimensional ortwo-dimensional capacitive micro-machined ultrasonic transducer (CMUT)array with supporting frame, the wafer bonding steps are replaced withsacrificial layer releasing steps.

BRIEF DESCRIPTION OF THE FIGURES

The objectives and advantages of the present invention will beunderstood by reading the following detailed description in conjunctionwith the drawing, in which:

FIG. 1 shows a schematic cross-section planar view of a prior art trenchisolated CMUT without supporting frame.

FIGS. 2 a-2 b show a schematic cross-section planar view and aperspective cutaway view of a trench isolated CMUT with supporting frameaccording to the present invention.

FIG. 3 shows the calculated parasitic capacitance as a function of BOXlayer thickness for a 200-μm thick SOI wafer with a frame width of 30 μmand a trench width of 30 μm according to the present invention.

FIG. 4 shows the measured and calculated parasitic capacitance valuesdue to the frame structure of a trench isolated CMUT with supportingframe according to one embodiment of the invention.

FIG. 5 shows the expected resistance values of an electrode for varioussubstrate resistivities of a trench isolated CMUT with supporting frameaccording to one embodiment of the invention.

FIGS. 6 a-6 j show a process flow for a method of creating a trenchisolated CMUT with supporting frame according to the present invention.

FIGS. 7 a-7 b show the typical real and imaginary parts of the inputimpedance according to the present invention.

FIG. 8 Shows the resonant frequency as a function of DC bias voltageaccording to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Although the following detailed description contains many specifics forthe purposes of illustration, anyone of ordinary skill in the art willreadily appreciate that many variations and alterations to the followingexemplary details are within the scope of the invention. Accordingly,the following preferred embodiment of the invention is set forth withoutany loss of generality to, and without imposing limitations upon, theclaimed invention.

FIG. 1 shows a schematic cross-section planar view of a prior art trenchisolated CMUT without supporting frame 100. Shown is a prime siliconwafer 101 having a silicon layer 102 of bulk silicon holding an oxidelayer 104 having CMUT cell cavities 106 covered with a membrane/topmetal layer 108 as a conductive front electrode, where the bulk silicon102 is a back electrode. The conductive bulk silicon 102 has anisolation trench 112 for separating the array elements 116 for improvedarray performance.

Typically, a carrier wafer (not shown) is required during the deepreactive ion etching (DRIE) and the flip-chip bonding steps to providethe mechanical support for the membranes 106. This particularrequirement presents certain drawbacks in processing. Good adhesionbetween the carrier wafer and the surface of the membrane 106 isrequired for adequate mechanical support for the membranes 106. However,it is difficult to separate the carrier wafer (not shown) and themembrane 106 after the flip-chip bonding. The adhesive material may alsoswell in the solvent, creating stress that can break the CMUT membranes106. It is highly desired to eliminate the need of the carrier wafer forthe trench isolation process. Further, in frameless trench-isolated CMUTarrays 100, only a few microns of silicon 108 and silicon dioxide (oxidelayer 104) remain between array elements 116 after the DRIE process.These thin-films are fragile and present handling difficulties. Thecarrier wafer is therefore needed for additional mechanical supportduring DRIE and flip-chip bonding steps.

FIGS. 2 a and 2 b show a schematic cross-section planar view and aperspective cutaway view, respectively, of a trench isolated CMUT withsupporting frame 200 according to the present invention. One-dimensionaland two-dimensional capacitive micro-machined ultrasonic transducer(CMUT) arrays 200 are provided. The invention includes a CMUT array on asilicon-on-insulator (SOI) wafer 201 using either wafer-bonding orsacrificial release techniques. The SOI wafer 201 has a conductivesubstrate 102 holding a device layer 203. Preferably, the device layer203 and the buried-oxide (BOX) 214 layer of the SOI wafer 201 are thick,and the conductivity of both the device layer 203 and handle (bulk)layer 102 of the SOI wafer 201 is high. The device layer 203 has anoxide insulation layer 205 disposed thereon to enable the cells 106 tooperate in a collapsed-mode (not shown) without short-circuiting. Theelectrical interconnects to the CMUT array elements 116 are providedthrough the highly conductive silicon substrate 102. A deepthrough-wafer trench 112 provides isolation, and a frame structure 202provides mechanical support for the rigidity of the CMUT array 200.Neighboring array elements 116 are separated from one another by devicetrenches 208 and bulk silicon trenches 112. On each element 116, thedevice layer 203 and the silicon bulk 102 are electrically connected byetching vias 212 through the oxide layer 214 and depositing conductivematerials therein. The frame 202 is made of bulk silicon and isgenerally at a different electrical potential than the back electrode110.

Parasitic parallel capacitance is reduced by using a thick BOX layer 214in the SOI wafer 201, etching wider trenches 112 between the electrode206 and the frame 202, reducing the frame width 202 and reducing thebulk layer 102 thickness. The series resistance of the interconnect canbe reduced by using a highly conductive silicon substrate 102 and bythinning down the substrate 102.

Because the isolation trenches 112 are formed after the CMUT membranes106 have been fabricated on the front side of the wafer 201, thethrough-wafer trench-isolation process is compatible with both thesurface micromachining and wafer-to-wafer fusion bonding techniques.

Using a supporting frame 202 with the trench isolated CMUT arrayspreserves the advantages of the frameless trench isolation process 100,such as the compatibility with both wafer-bonding and surfacemicromachining processes, and eliminates the need of a carrier wafer. Itis therefore an important enabling technology for the advancement of 1Dand 2D CMUT arrays.

Instead of the carrier wafer (not shown), the trench-isolated CMUTarrays with a supporting frame 200 have a built-in silicon meshstructure 202 disposed between the array elements 116 to provide theneeded mechanical support. A cross-sectional view is shown in FIG. 2(a)and a 3D perspective diagram of the supporting frame is shown in FIG.2(b). Both the supporting frame 202 and the signal electrodes 206 arebuilt into the substrate 102 of a highly conductive SOI wafer 201. Deepthrough-wafer trenches 112 are etched from the back side of the SOIwafer 102 to separate the frame 202 and the signal electrodes 206. Thefront electrical pads 210 are electrically divided by device layertrenches 208 etched on the device layer 203 of the same SOI wafer 201. Avia 212 is etched on the device layer silicon 203 and the buried oxide(BOX) layers 214 so that conductive material 110, such as aluminum, canbe deposited into the via 212 to bring electrical continuity for thesignal electrodes 206. Electrode separation trenches 216 are formed inthe conductive material 110 deposited in the vias 212 to isolate the topelectrode 110 from the signal electrodes 206. In the trench-isolatedCMUT arrays with supporting frames 200, the parasitic capacitance islargely determined by the overlapping areas between the device layer 203and bulk layer 102 of the SOI wafer 201. Therefore, the parasiticcapacitance can be reduced by increasing the BOX layer 214 thickness andby reducing the width of the mesh frames 202. The inventors havedetermined that SOI sample pieces with frames 202 as narrow as 10 μmcould be handled like regular pieces of silicon. The thickness of theBOX layer 214 can be easily made to 4-5 μm thick in a wet oxidationenvironment at 1100° C. for 48 hours.

FIG. 3 shows a graph of the calculated parasitic capacitance as afunction of BOX layer 214 thickness for a 200-μm thick SOI wafer 102with a frame width of 30 μm. As shown in FIG. 3, the parasiticcapacitance can be reduced to an insignificant level by design, assumingthe device capacitance of an array element is in the order of 1 pF.

To confirm the calculation of the parasitic capacitance, test dummydevices consisting of mesh frames 202 and front side electrical pads 210were fabricated on an SOI wafer 102 with an 8-μm device layer 203 and0.2-μm BOX layer 212. FIG. 4 shows a graph of the measured andcalculated capacitance values. One possible explanation for the smallermeasured capacitance than the calculated capacitance is the footingphenomenon of the DRIE when the etching is terminated on oxide. Footingreduces the effective overlapping areas between the signal electrode 206and ground electrodes 110 and thus results in lower parasiticcapacitance. Series resistance is a function of the size of the signalelectrode 206 and the resistivity of the silicon substrate 102. Toreduce the series resistance, a highly conductive substrate is desired.FIG. 5 shows the expected resistance values of an electrode for varioussubstrate resistivities. When a highly conductive substrate 102 is used,the series resistance can be ignored. Because a contact via 212 isneeded in the device layer 214 to make electrical continuity for theinterconnects, the fill factor of the CMUT is affected. This isanalogous to the reduction of fill factor in CMUTs with through-wafervia interconnects. This impact of fill factor is compensated by the factthat the isolation trench 208 on the front side of the device layer 203can be narrow (a few microns) because this layer 203 is relatively thinand definition of narrow trenches 208 is possible using DRIE. A fillfactor of 0.72 has been achieved by the inventors.

FIGS. 6 a-6 j show process flow for fabricating the device 600 describedabove. CMUT cell cavities 106 are first defined on the device layer 203of the SOI wafer 201 using oxidation and buffered oxide etching (BOE)techniques, where the device layer 203 has a has an oxide insulationlayer 205 disposed thereon to enable the cells 106 to operate in acollapsed-mode (not shown) without short-circuiting (FIG. 6 a). Thefront electrical pads 210 are then electrically divided in a DRIE step,where the array elements 116 are separated from one another by etchingseparation trenches 208 on the device layer 203 (FIG. 6 b). Next,another SOI wafer 201 with a membrane silicon layer 108 is fusion bondedto the device side 203 of the first SOI wafer 201 and annealed at 1000°C. for 30 minutes (FIG. 6 c). The handle wafer 102 of the second SOIwafer 201 is removed in a heated tetramethylammonium hydroxide solution(FIG. 6 d). A contact via 212 on each array element 116 is defined byphoto lithography and wet etching of silicon in heated potassiumhydroxide (KOH) solution using the BOX layer 212 of the second SOI waferas the hard mask (FIG. 6 e). This etching step stops automatically (notshown) at the BOX layer 214 underneath the device layer 203.Alternatively, a DRIE can be used for this etching step. A dry plasmaetcher is used to remove the recessed BOX layer (not shown) in the viaregion. In this step, the exposed silicon 102 resulting from the KOHetching step serves as the hard mask. An aluminum layer is thensputtered on the membrane of the cells 106 to form the top electrode110, as well as on the contact via 212 to establish electricalcontinuity for the signal electrodes 110 (FIG. 6 f). The siliconsubstrate is thinned down to 200 μm by mechanical grinding and polishing(not shown). The front and back electrodes (see FIG. 6 i) are separatedfrom each other by providing electrode separation trenches 216 fromremoving conductive materials around the contact vias (FIG. 6 g). A7-μm-thick photo resist layer is spin-coated onto the back side of theSOI wafer and patterned (not shown). Through-wafer trenches 112 areetched on the bulk silicon wafer 102 for electrical isolation and todefine the supporting frame 202 (FIG. 6 h) as well as the signalelectrodes. A layer of Ti/Cu/Au is evaporated onto the electrodes toenhance the electrical contact to the silicon (FIG. 6 i). Duringevaporation, the wafer is tilted for 45° to prevent electrical shortingbetween neighboring elements (not shown). The CMUT arrays 200 are nowready to be flip-chip bonded 602 to the appropriate electronic circuitsor printed circuit boards 604 (FIG. 6 j).

The inventors fabricated trench-isolated, 2D, 16-element×16-element,CMUT arrays with supporting frames 200 to demonstrate the feasibility ofthis technique. A summary of the device parameters is shown in Table I.TABLE I DEVICE PARAMETERS FOR TRENCH-ISOLATED CMUT ARRAY WITH ASUPPORTING FRAME. Membrane Width (μm) 40 Membrane Length (μm) 140 Numberof Membranes/Element 8 Element Pitch (μm) 250 Membrane Thickness (μm)1.84 Cavity Height (μm) 0.15 Substrate Thickness (μm) 200 Device LayerThickness (μm) 10 BOX Layer Thickness (μm) 1.95 Trench Width (μm) 50Frame Width (μm) 30 Silicon Wafer Resistivity (Ω-cm) 0.025

Electrical input impedance in air was measured by probing the signalelectrodes on the finished devices using a network analyzer. FIGS. 7(a)and 7(b) show the typical real and imaginary parts of the inputimpedance. The resonant frequency as a function of DC bias voltage isshown in FIG. 8. The collapse voltage is found to be 80 volts,reasonably close to the predicted value of 82 volts. Across the array,the resonant frequency is uniform. The standard deviation is 0.02 MHz(0.23%). The inventors have successfully demonstrated devices with 16×16elements in the array functioning.

The total device capacitance is measured to be 1.9 pF. Based on thedesign parameters, the predicted device capacitance is calculated to be1.66 pF, and the parasitic capacitance is calculated to be 0.29 pF.Therefore, the total measured capacitance agrees with the theoreticalprediction.

1D and 2D CMUT arrays with a supporting frame have been demonstrated.Through-wafer trench-isolated interconnects are implemented on thesesarrays. The finished wafers can be handled like regular wafers. Thefabrication process is compatible with both the surface micromachiningand the wafer bonding processes developed for CMUTs because the trenchesare fabricated after the formation of the CMUT membranes. The overallprocess is simple, and results in good device uniformity. These CMUTdevices have a parasitic capacitance that is negligible when compared tothe device capacitance. In air testing, the predicted resonant frequencyand collapse voltage are reasonably close to the predicted values.

The present invention has now been described in accordance with severalexemplary embodiments, which are intended to be illustrative in allaspects, rather than restrictive. Thus, the present invention is capableof many variations in detailed implementation, which may be derived fromthe description contained herein by a person of ordinary skill in theart. For example, one variation pertains to trench isolation patterns,where the patterns can be regular tessellations such as triangle, squareand hexagonal. Other variations pertain to the trench isolationpatterns, thickness, depth and geometry being arranged in any otherconfiguration dictated by their application, bandwidth and powerrequirements.

All such variations are considered to be within the scope and spirit ofthe present invention as defined by the following claims and their legalequivalents.

1. A one-dimensional or two-dimensional capacitive micro-machinedultrasonic transducer (CMUT) array with supporting frame comprising: a.at least three CMUT array elements deposited on a conductive substrate;b. at least one CMUT cell in said array element; c. a conductive toplayer deposited to a top side of said element; d. a conductive viadisposed within said elements, wherein said via is isolated from saidconductive top layer and conducts with said substrate; e. at least twoisolation trenches in said conductive substrate, wherein said trenchesare disposed between adjacent said vias, whereby conductively isolatingsaid vias, whereas a substrate region between said trenches forms amechanical support frame; and f. at least one conductive electrodedeposited to a bottom surface of said conductive substrate, wherein saidelectrode is disposed to conduct with said via.
 2. The CMUT array withsupporting frame of claim 1, wherein said conductive substrate comprisesa silicon-on-insulator wafer, whereby said wafer comprises a siliconoxide layer on a silicon layer.
 3. The CMUT array with supporting frameof claim 1, wherein said conductive top layer comprises a conductivematerial selected from a group consisting of aluminum, titanium,tungsten and polysilicon.
 4. The CMUT array with supporting frame ofclaim 1, wherein said conductive top layer is omitted when said top sideof said element comprises as highly conductive silicon membrane.
 5. TheCMUT array with supporting frame of claim 1, wherein said conductive viacomprises a conductive material selected from a group consisting ofaluminum, polysilicon and amorphous silicon.
 6. The CMUT array withsupporting frame of claim 1, wherein said conductive electrode isselected from a group consisting of copper, titanium, gold, platinum,aluminum and nickel.
 7. A method of fabricating a one-dimensional ortwo-dimensional capacitive micro-machined ultrasonic transducer (CMUT)array with supporting frame comprising: a. providing adouble-side-polished silicon-on-insulator wafer; b. etching CMUTcavities in a device layer of said wafer using oxidation and bufferedoxide etching methods; c. electrically dividing front electrical pads onsaid wafer using deep reactive ion etching; d. bonding a second saidsilicon-on-insulator wafer to said etched device layer; e. removing ahandle layer of said second silicon-on-insulator wafer; f. providing acontact via on each array element of said CMUT array using photolithography and wet etching or dry etching; g. depositing a conductivetop electrode material on said etched wafer; h. removing said conductivematerial around said vias to separate front and back electrodes fromeach other; i. etching through-wafer trenches on said silicon wafer forelectrical isolation and to define a supporting frame; j. patterningsignal electrodes on said back electrodes; and k. flip-chip bonding CMUTarrays to appropriate electronic circuits or printed circuit boards. 8.The method of claim 7, wherein said wafer bonding steps are replacedwith sacrificial layer releasing steps.